Data extracting circuit for serial control apparatus

ABSTRACT

A serial control apparatus includes a main controller (2) and a plurality of nodes (3) each serving as an auxiliary controller normally serially arranged on a loop-shaped signal transmission line (1). Each node (3) extracts data for the present node among from the data delivered from the main controller (2) as time elapses so as to allow the terminal units (A) associated with the present node to be properly controlled. In addition, the node inserts the output data from the terminal units (A) into a time slot corresponding to the present node and then delivers to the signal transmission line (1) the output data which in turn are transferred to the main controller (2) via other nodes on the downstream side. To assure that the data extracting circuit operates properly, two latching circuits, i.e., first and second latching circuits (311, 312 to 315) are serially arranged in a signal passage by way of which the extracted data are fed to a driver (316) for the corresponding terminal units.

TECHNICAL FIELD

The present invention relates to a data extracting circuit preferablyemployable for a serial control apparatus which has been hitherto usedfor a central control system available for various kinds of machinessuch as a press, a machine tool, a construction machine, a ship, anaircraft or the like machine as well as a central control systemavailable for an unmanned conveying unit, an unmanned warehouse or thelike installation.

BACKGROUND ART

When presses, machine tools, construction machines, ships, aircrafts,unmanned couveying units, unmanned warehouses or the like are to becentrally controlled, a large number of sensors for detecting thepresent operative state of each section in these machines orinstallations and a large number of actuators for controlling thepresent operative state of each section in these machines orinstallations are required. For example, in the case of a press, thenumber of required sensors and actuators exceeds 3000. In other case,each machine or installation may need to be equipped with sensors andactuators more than 3000 in number.

Hitherto, the central control system for centrally controlling theforegoing kinds of machines or installations is typically constructedsuch that a number of sensors and a number of actuators are connected toa main controller so that a number of sensor outputs are collected inthe main controller which in turn controls the actuators.

With the conventional central control system as constructed in theabove-described manner, as a large number of sensors and actuators arerequired, the number of connection lines extending between the maincontroller and the sensors/actuators increases enormously. In addition,an input/output section in the main controller becomes unavoidablycomplicated in structure.

To obviate the foregoing problem, a proposal has been made such that aplurality of nodes are serially arranged one after another, one or aplurality of sensors and actuators are connected to each node and thenodes are connected to each other via a main controller so that eachnode is properly controlled in response to a signal outputted from themain controller. With such a structure as described above, the maincontroller is basically required to have a plurality of signal inputlines and a plurality of signal output lines by way of which the maincontroller is connected to the respective nodes, resulting in the numberof wiring lines being reduced substantially.

However, in a case where the central control system is constructed suchthat the nodes are serially connected to each other, there arises aproblem as to how simultaneous collection of outputs from the respectivenodes and simultaneous control of the respective actuators areaccomplished. For example, in the case of a structure wherein a specificaddress is allocated to each node to control the latter based on theallocated address, time delay caused by processing a plurality ofallocated addresses becomes another problem. Thus, simultaneouscollection of outputs from the respective sensors and simultaneouscontrol of the respective actuators cannot be accomplishedsatisfactorily.

In view of the aforementioned facts, the inventors abandoned thetechnical concept that a plurality of nodes are serially connected toeach other with a specific address allocated to each node. Instead ofthe foregoing technical concept, the inventors propose a serial controlapparatus which is constructed such that each node is distinguished fromother node in accordance with an order of node connection. With thisproposed serial control apparatus, any address processing is notrequired and time delay caused by the address processing is eliminatedwith the result that a node structure can be simplified remarkably.

The proposed serial control apparatus is constructed such that each nodesuccessively adds output signals from sensors in the present node to asignal from nodes on the upstream side in compliance with apredetermined rule and signals specifically intended for the presentnode are successively extracted from among signals transmitted fromnodes on the upstream side so that the former signals are outputted to aplurality of actuators associated with the present node. With the serialcontrol apparatus, each node does not require not only any address butalso a step of address processing, causing time delay at each node to bereduced to such a very small quantity that merely a timing coincidenceis required. Additionally, a node structure is largely simplified.

FIG. 1 is a block diagram which schematically illustrates by way ofexample the aforementioned serial control apparatus. As is apparent fromthe drawing, the serial control apparatus includes a main controller 2and n nods 3 - 1 to 3 - n both of which are arranged along a loop-shapedsignal transmission line 1, and each of the nodes 3 - 1 to 3 - n has aplurality of sensors Sl to Si and a plurality of actuators Al to Akconnected thereto.

As shown in FIG. 2(a), the main controller 2 sends a communicationinformation to the signal transmission line, wherein the communicationinformation includes a start code ST at the head end, a controlinformation DATA for each node at the subsequent location, a stop codeSP indicative of the end of the control information DATA at thesubsequent location and an error check code ERC such as a parity checkcode, a CRC code or the like at the tail end. The communicationinformation is serially transmitted to the respective nodes 3 - 1 to 3 -n via the signal transmission line 1.

When each of the respective nodes 3 - 1 to 3 - n receives acommunication information via the signal transmission line 1, itextracts a control information on a time slot corresponding to aspecific connection number allocated to the present node and thencontrols the actuators Al to Ak in accordance with the controlinformation. Then, each node inserts output signals for the sensors Slto Si into a time slot associated with the connection number allocatedto the present node, and the output signals are transmitted to nodes onthe downstream side.

Therefore, when the control information DATA transmitted from the maincontroller 2 is outputted from the node 3 - n on the ultimate downstreamside (see FIG. 2(e)), it is converted into a sensor output signal foreach node. In response to the sensor output signal, the main controllerdetects the present operative state of each of the nodes 3 - 1 to 3 - n.Then, the process goes to a next control step.

Referring to FIG. 2 again, T₀₁, T₀₂, T₁₁, - - - represent a signaltransmission time of the corresponding signal, respectively. With theillustrated serial control apparatus, it is assumed that transmission ofa series of signals S0 to Sn shown in FIG. 2 is repeatedly carried outat a high speed in accordance with the following relationship. ##EQU1##

When such a serial control apparatus as described above is employed, asignal frame as shown in FIG. 2 is used as a signal to be transmittedthrough the respective nodes 3 - 1 to 3 - n and moreover theaforementioned protocol is additionally employed for the serial controlapparatus. Thus, data receiving/transmitting and error check cancertainly and effectively be accomplished with the serial controlapparatus. However, in a case where a certain machine is to becontrolled with the serial control apparatus via, e.g., a plurality ofactuators as mentioned above, there is liable to arise a malfunctionthat informations are erroneously outputted to the actuator and therebyincorrect operation of the machine to be controlled is induced.

The present invention has been made with the foregoing background inmind and its object resides in providing a data extracting circuitemployable for a serial control apparatus which can reliably prevent aplurality of actuators or the like from being erroneously actuated andmoreover assures that a machine to be controlled is properly operatedwith a high reliability.

DISCLOSURE OF THE INVENTION

According to the present invention, e.g., first and second latchingmeans are serially arranged in a signal passage by way of which dataextracted from each node are fed to a driver for corresponding terminalunits (actuators). In a case where an error or an error history isdetected when the data are to be transferred, the data extractingcircuit inhibits the data from being latched in the latching meansdisposed on the driver side, whereby erroneous data or uncertain dataare not fed to the driver without fail.

By doing so, at least an erroneous operation of the actuators or thelike due to an error during data transmission is prevented.

In addition, according to the present invention, the data extractingcircuit determines with a predetermined logic based on plural latchingoperations performed by the first and second latching means whether dataextracted at every data extracting operation are true or false. Further,the data extracting circuit is additionally provided with determiningmeans for permitting only the data which have been determined as truedata to be inputted into the driver.

Thus, the data extracting circuit can detect any data error even in thefollowing cases and thereby can realize terminal control with a highreliability: (a) a case where the main controller sends as control dataa plurality of data which have been originally erroneous, and (b) a casewhere one of data in an inputted data row is outputted with a logicalcontent of the data inverted because of incorrect operation performed ateach node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram which illustrates by way of example astructure of a serial control apparatus to which the present inventionis applied.

FIG. 2 shows a plurality of time charts each of which illustrates by wayof example a pattern representative of a signal frame employable for theserial control apparatus.

FIG. 3 is a block diagram which schematically illustrates a dataextracting circuit in accordance with an embodiment of the presentinvention.

FIG. 4 and FIG. 5 show a plurality of time charts each of whichillustrates by way of example operations to be performed by the dataextracting circuit shown in FIG. 3, respectively.

FIG. 6 is a block diagram which schematically illustrates a dataextracting circuit in accordance with another embodiment of the presentinvention.

FIG. 7 is a block diagram which schematically illustrates by way ofexample a concrete structure of a collating block shown in FIG. 6.

FIG. 8 is a time chart which illustrates by way of example a data bitsignal to be inputted into the collating block.

FIG. 9 is a schematic view which comparatively illustrates a pattern ofa normal signal frame and a pattern of a signal frame in the event ofline disconnection in conjunction with a data extracting circuit inaccordance with another embodiment of the present invention.

FIG. 10 is a block diagram which schematically illustrates a structureof the data frame circuit in accordance with the latter embodiment ofthe present invention.

FIG. 11 shows a plurality of time charts each of which illustrates byway of example operations to be performed by the data extracting circuitshown in FIG. 10.

FIG. 12 is a block diagram which schematically illustrates by way ofexample a structure of the data extracting circuit in a main controllerin accordance with the embodiment of the present invention in FIG. 10.

FIG. 13 shows a plurality of time charts each of which illustrates byway of example operations to be performed by the data extracting circuitshown in FIG. 12.

FIG. 14 is a block diagram which schematically illustrates by way ofexample other structure of the data extracting circuit in the maincontroller in accordance with the embodiment of the present invention inFIG. 10.

FIG. 15 and FIG. 16 are each a schematic view which particularlyillustrates variation of an information on a trouble of linedisconnection to be delivered from the data extracting circuit in theevent of line disconnection as well as at the time when a repairingoperation is performed for eliminating the trouble of line disconnectionto return to a normal condition, respectively.

FIG. 17 shows a plurality of time charts each of which illustrates byway of example operations to be performed by the data extracting circuitshown in FIG. 14.

BEST MODE FOR CARRYING OUT THE INVENTION

FIGS. 3 to 5 illustrate a data extracting circuit employable for aserial control apparatus in accordance with an embodiment of the presentinvention.

FIG. 3 is a block diagram which schematically illustrates by way ofexample a concrete structure of each of nodes 3 - 1 to 3 - n eachserving as an auxiliary controller for the serial control apparatus onthe assumption that the serial control apparatus is typicallyconstructed as schematically illustrated in FIG. 1. For the convenienceof easy understanding of the present invention, it is assumed that allthe node 3-1 to 3-n are used for controlling their correspondingacutators, and they are constructed in a common structure.

Referring to FIG. 3, each of the nodes 3-1 to 3-n includes an inputcircuit 301 into which a signal transmitted from a main controller 2 ora node at the preceding stage is inputted so as to allow the inputsignal to be demodulated as desired, a start code detecting circuit 302in which the aforementioned "start code ST" indicative of the head endof a data row DATA is detected from the demodulated input signal with apredetermined logic structure, a stop code detecting circuit 303 inwhich the aforementioned "stop code SP" indicative of the tail end ofthe data row DATA is likewise detected from the demodulated input signalwith another predetermined logic structure, an error check codeinspecting circuit 304 in which presence or absence of an error that mayoccur between the preceding stage (preceding port) and the present stage(present port) is inspected based on the aforementioned "error checkcode ERC (to be generated and then outputted as an aforementioned codefor retrieving presence or absence of an error via an error check codegenerating circuit 308 to be described later wherein the error checkcode generating circuit 308 is included in nodes peripheral to the nodeat the preceding stage)" derived from the demodulated input signal, anerror code detecting circuit 305 for monitoring whether or not theaforementioned "error code ER (to be generated and added based ondetection of an error occurrence via an error code adding circuit 309 tobe described later wherein the error code adding circuit 309 is includedin nodes peripheral to the node at the preceding state)" is added inorder to inform an error occurrence to the demodulated input signal andthen informing addition of the error code ER when it is found that theerror code ER has been added, a data row length detecting circuit 306 inwhich a length of a data row extending between the "start code ST" andthe "stop code SP" associated with the demodulated input signal isobtained in response to detection of the "start code ST" and the "stopcode" so that presence or absence of an error occurrence is detecteddepending on the fact as to whether the obtained data row length is anadequate length or not, an OR circuit OR in which a logical sumcomprising an error detecting output derived from the error check codedetecting circuit 304, an error code detecting output derived from theerror code detecting circuit 305 and a detecting output derived from thedata row length inspecting circuit 306 in respect of an abnormality withthe data row length is received, a data extracting circuit 307 in whichcontrol data for a plurality of corresponding actuators are extractedfrom the demodulated input signal (more exactly speaking, a data rowincluded in the demodulated input signal), an error check codegenerating circuit 308 in which a new "error check code ERC" isgenerated in response to the demodulated input signal and from which thenew "error check code ERC" is outputted, a switch circuit SW1 forcontrolling the demodulated input signal to be inputted into the errorcheck code generating circuit 308 in an opened/closed (ON/OFF) state, anerror code adding circuit 309 in which the aforementioned "error code"is generated and is added to the demodulated input signal as desired (byselecting a switch circuit SW2 to be described later), a switch circuitSW2 for selecting either one of the demodulated input signal, a signal(error check code ERC) to be generated and outputted from the errorcheck code generating circuit 308 and a signal (error code ER) to beoutputted from the error code adding circuit 309 as time elapses, anoutput circuit 310 in which a signal selectively outputted from theswitch circuit SW2 is modulated as desired and from which the modulatedsignal is transmitted to a node at the subsequent stage or a maincontroller, a data latching circuit 311 in which the control dataextracted from the data extracting circuit 307 are latched on closure(ON) of the switch circuit SW2, first to fourth latching circuits 312 to315 in which the control data latched in the data latching circuit 311are successively shifted on closure (ON) of the switch circuits SW1 toSW2 and they are then latched, a driver 316 in which a driving signalfor driving a corresponding actuator is generated based on the datawhich have been latched in the fourth latching circuit 315 that is alatch circuit at the final stage among an array of latching circuits andfrom which the generated driving signal is outputted, an innercontroller 317 for centrally controlling opening/closing (ON/OFF) or amanner of shifting each of a plurality of switch circuit SW1, SW2, SW3,SWL1, SWL2 and SWL3 in response to a detecting output from the startcode detecting circuit 302 and the stop code detecting circuit 303, alogical sum output from the OR circuit OR and a signal representative ofcompletion of outputting from the error check code generating circuit308 and the error code adding circuit 309 in respect of the "error checkcode ERC" and the "error code ER" , and a comparing circuit 318 in whichthe contents of latching operations performed by the first to thirdlatch circuits 312 to 314 constituting an array of latching circuits issimultaneously compared with each other and the switch circuit SWL4 isopened (turned on) under a condition that all contents of latchingoperations are identical to each other.

In detail, in a case where receiving/transferring of a signal betweenadjacent nodes are effected via a cable made of metallic material (twitspair cable, coaxial cable or the like cable), the input circuit 301 isconstructed such that it includes an impedance matching circuit, aninput amplifier, a demodulating circuit and others. Alternatively, in acase where receiving/transferring of a signal therebetween is effectedvia an optical fiber, the input circuit 301 may be constructed such thatit includes an optical/electrical converter, a demodulating circuit(Manchester demodulating circuit, CMI demodulating circuit or the likecircuit).

Next, in a case where receiving/transferring of a signal between therespective nodes is serially effected, the output circuit 310 islikewise constructed such that it includes a demodulating circuit, adriver circuit and others. Alternatively, in a case where signalreceiving/transferring is optically effected, the output circuit 310 maybe constructed such that it includes a demodulating circuit, anelectrical/optical converter or the like circuit.

The error check code inspecting circuit 304 comprises a hitherto knowncircuit for carrying out error check in accordance with CRC checkingsystem, a vertical/horizontal parity checking system or the like system.

According to the embodiment of the present invention, the innercontroller 317 comprises a controller which is constructed with its owncontrol logic previously incorporated therein such that the switchcircuit SW1 is closed (turned on) in response to output representativeof detection of the "start code ST", the switch circuit SW3 is closed(turned on) for a predetermined period of time which is related toextraction of control data and moreover it is operated so as to allowthe switch circuit SW1 to be restored to an opened state (OFF state) inresponse to output derived from detection of the "stop code SP" when thelatter is detected, and the switch circuit SW2 shifts the initialselected state of "0-1" to another selected state of "0-2", that when asignal representative of completion of outputting of the "error checkcode ERC" is outputted from the error check code generation circuit 308,the switch circuit SW2 which has assumed the selected state of "0-2" isrestored to the selected state of "0-1" and moreover the switch circuitSW2 is successively closed (turned on) for a predetermined period oftime in accordance with an order of the switch circuit SWL3→the switchcircuit SWL2→the switch circuit SW1, that when a signal representativeof completion of outputting of the "error check code ERC" is outputtedfrom the error check code generating circuit 308, the switch circuitsSWL1 to SWL3 are opened (turned off), when it is found that an outputrepresentative of a logical sum derived from the OR circuit OR is keptat a level of logic "1", and that merely the switch circuit SW2 whichhas assumed the selected state of "0-2" is once shifted to the selectedstate of "0-3" and thereafter it is restored to the selected state of"0-1" under a condition that a signal representative of completion ofadding of the "error code ER" is outputted from the error code addingcircuit 309. Here, a manner of controlling the respective switchcircuits as mentioned above with the inner controller 317 is illustratedin Table 1.

                  TABLE 1                                                         ______________________________________                                        detection  detection completion                                                                              completion                                     of start   of stop   of trans- of adding                                      code       code (com-                                                                              ference of                                                                              of error                                                  pletion of                                                                              error check                                                                             code                                                      inspection                                                                              code                                                                of data row                                                                   length)                                                             ##STR1##                                                                                 ##STR2##                                                                                ##STR3##                                                                                ##STR4##                                      SW1   opened   closed    opened  opened  closed                                     (OFF)    (ON)      (OFF)   (OFF)   (ON)                                                                  (output                                                                       from OR                                            0 - 1    0 - 1     0 - 2   = "0")  0 - 1                                                                 0 - 1                                        SW2                              (output                                                                       from OR                                                                       = "1")                                                                        0 - 3                                              opened   closed for                                                                              opened  opened  opened                                     (OFF)    predeterm (OFF)   (OFF)   (OFF)                                SW3            ned period                                                                    of time                                                                       (ON)                                                                                            (output                                                                       from OR                                                                       = "0"                                               opened   opened    opened                                                                                ##STR5##                                                                              opened                                    (OFF)    (OFF)     (OFF)   (output (OFF)                                SWL1                             from                                                                          = "1")                                                                        opened                                                                        (OFF)                                                                         (output                                                                       from OR                                                                       = "0")                                                                         ##STR6##                                                                     OFF                                          SWL2  opened   opened    opened  (output opened                                     (OFF)    (OFF)     (OFF)   from OR (OFF)                                                                 = "1")                                                                        opened                                                                        (OFF)                                                                         (output                                                                       from OR                                                                       = "0")                                                                         ##STR7##                                    SWL3  opened   opened    opened  (output opened                                     (OFF)    (OFF)     (OFF)   from OR (OFF)                                                                 = "1")                                                                        opened                                                                        (OFF)                                        ______________________________________                                    

It should be noted that the main controller 2 for the serial controlapparatus repeatedly transfers as a data row DATA a plurality of controldata each having a same content to the node 3-1 at the first stage untilthere arises a necessity for updating the content of control to becarried out for each actuator.

FIG. 4 and FIG. 5 are a plurality of time charts each of whichillustrates by way of example operations to be performed by the node 3-2among the nodes 3-1 to 3-n, respectively. Signal processing operationsand data extracting operations to be executed by the node 3-2 will bedescribed in more detail below with reference to FIG. 4 and FIG. 5. Aswill be apparent from FIG. 4 and FIG. 5, according to the embodiment ofthe present invention, a method of transferring signals between adjacentnodes without time delay is employed for the data extracting circuitemployable for the serial control apparatus.

Now, it is assumed that a signal is transmitted from the node at thepreceding stage (node 3-1) to the node at the subsequent stage (node3-2) in such a manner as shown in FIG. 4(a) in response to an occurrenceof error during data transmission between the main controller 2 and thenode 3-1. The inner controller 317 controls a shifting operation to beperformed toward the ON side for the switch circuit SW1 which has beeninitially shifted to the OFF side, when the the "start code ST" isdetected by the start code detecting circuit 302. Then, the error checkcode generating circuit 308 starts an operation for generating an errorcheck code ERC to be transferred to the node at the subsequent stage(node 3-3) in response to the signal which has been inputted in thatway. At this time, the switch circuit SW2 is held at the initial stateas shown in FIG. 4(c) (selected state of "0-1") wherein the signal isselectively inputted into a terminal 1. The start code ST and the datarow DATA are added to the output circuit 310 via the switch circuit SW2as they are, and thereafter they are outputted to the node at thesubsequent stage (node 3-3) as a signal S2 via the output circuit 310(see FIG. 4(i)). In the meantime, the data extracting circuit 307executes extraction of control data for controlling a correspondingactuator. The thus extracted control data are latched in the datalatching circuit 311 as the switch circuit SW3 performs an ON operationin such a manner as shown in FIG. 4(d).

In response to the signal which has been transferred as shown in FIG.4(a), the stop code detecting circuit 303 detects the "stop code SP"which is associated with the foregoing signal.

When the stop code detecting circuit 303 detects the "stop code" in thatway, the inner controller 317 controls a shifting operation for shiftingthe switch circuit SW1 to the initial OFF state of the switch circuitSW1 and moreover shifting the switch circuit SW2 to the selected statewherein the signal is selectively inputted into its terminal 2 (selectedstate of "0-2" (see FIGS. 4(b) and (c)).

On completion of the changing operation in the switch circuit SW2, the"error check code ERC2" which has been newly generated in the errorcheck code generating circuit 308 subsequent to the detected stop codeSP is selectively outputted from the switch circuit SW and thentransferred further via the output circuit 310 (see FIG. 4(i)).

In the meantime, in response to the signal which has been transferredfrom the node at the preceding stage (node 3-1), the error check codeinspecting circuit 304, the error code detecting circuit 305 and thedata row length inspecting circuit 306 execute an inspecting operationin such a manner as mentioned above. As a result, the error codedetecting circuit 305 detects at least based on its detection of the"error code ER" that some data error has previously occurred. A resultderived from the foregoing detection is transmitted to the innercontroller 317 via the OR circuit OR.

Therefore, in this case, at the same time when a signal representativeof completion of outputting from the error check code generating circuit308 is issued therefrom, the switch circuit SW2 is shifted to theselected state wherein the signal is selectively inputted into itsterminal 3 (selected state of "0-3"), and a signal to be outputted tothe output circuit 310 is added with an "error code ER" to be outputtedfrom the error code adding circuit 309 subsequent to the "error checkcode ERC2" which has been generated in and outputted from the errorcheck code generating circuit 308 (see FIGS. 4 (c) and (i)). In thiscase, since the inner controller 317 does not control any closingoperation for the switch circuits SWL 1 to SWL 3, the data which havebeen latched in the data latching circuit 311 are not received in thefirst latching circuit 312 and other subsequent circuits (see FIGS. 4(e)to (g)).

Thereafter, on completion of the adding operation in the error codeadding circuit 309, a signal representative of completion of the errorcode adding operation is issued to the inner controller 317. In responseto this signal, the inner controller 317 operates to shift the switchcircuit SW2 to the initial selected state wherein the signal isselectively inputted into its terminal 1 (see FIG. 4(c)).

As the node 3-2 operates in the above-described manner, the signal S2 tobe transferred from the node 3-2 to the node 3-3 at the subsequent stageis properly added with an "error code ER" for informing that the node3-2 is held in the state wherein an error has occurred. At this time,there is no possibility that control date associated with the foregoingerror are added to the corresponding actuator.

As exemplified in FIG. 5, in a case where no data abnormality isdetected in each error check code inspecting circuit 304, the error codedetecting circuit 305 and the data row length inspecting circuit 306,i.e., in a case where an output representative of a logical sum derivedfrom the OR circuit OR is held at a level of "0", the inner controller317 not only in the node at the preceding stage (node 3-1) but also inthe node at the present stage (node 302) operates such that the switchcircuit SW2 is shifted to the initial state of "0-1" as shown in FIG.5(c), when a signal representative of completion of outputting of the"error check code ERC2" which has been generated in the error check codegenerating circuit 308 is added to the inner controller 317, as shown inTable 1. In addition, the inner controller 317 operates such that theswitches SWL1 to SWL 3 are successively stepwise turned on for apredetermined period of time in an inverse order from the switch circuitSWL3 to the switch circuit SWL1, as shown in FIGS. 5(e) to (g).

Here, if a certain node (i.e., node 3-2) is particularly taken intoaccount, latched data are successively shifted from the latchingcircuits at the preceding state (inclusive of the data latching circuit311) to the latching circuit at the subsequent stage in the first tothird latching circuits 312 to 314 at every time when a frame signal(signal S1) as shown in FIG. 5(a) is inputted into the foregoing node.

The comparing circuit 318 comprises a circuit in which contents oflatching operations performed in the first to third latching circuits312 to 314 are simultaneously compared with each other and if it isfound that all the contents are identical to each other, the switchcircuit SWL4 is turned on in such a manner as represented by a dottedline in FIG. 5(h) so that the data latched in the third latching circuit314 are transferred to the fourth latching circuit 315, as mentionedabove. In detail, the comparing circuit 318 is operated such thatcontents of data to be transferred to a plurality of correspondingactuators are received by the driver 316 via the fourth latching circuit315 so as to allow the corresponding actuator to be practically drivenvia the driver 316 under a condition that the switch circuit SWL4 isturned on at the present node (node 3-2), i.e, under a condition thatcontents of all the control data latched in the respective first tothird latching circuits 312 to 314 by a quantity equal to three times(i.e., by a quantity equal to three frames) to be transferred to thecorresponding actuator are identical to each other.

Since each node operates in the above-described manner, even when therearises a data abnormality which can not be detected by error checkingmeans such as the error check code inspecting circuit 304, the errorcode detecting circuit 305 and the data row length inspecting circuit306 in the following typical cases, there is a substantial reduction inthe danger that the corresponding actuator is incorrectly controlledbased on abnormal data:

(a) a case where the main controller delivers as its control data thedata which have been originally erroneous, and

(b) a case where one datum among an inputted data row is outputted in aninverse state due to incorrect operations performed in each node.

Next, for the convenience of reference, a transition of latchingoperations performed in the first to fourth latching circuits 312 to 315in a certain node inclusive of a comparing operation to be performed bythe comparing circuit 318 (ON/OFF operations to be performed by theswitch circuit SWL4) is listed in Table 2 with respect to a case whereten signals corresponding to a frame 1 to frame 10 are inputted into thenode wherein desired control data each having a control contentcorresponding to a logic level of "1" are included in the frames 1 to 10for first to third signals and desired control data each having acontrol content corresponding to a logical level of "0" are includes fora fourth signal and subsequent signals.

                  TABLE 2                                                         ______________________________________                                              first   second  third       fourth                                      frame latch-  latch-  latch-                                                                              switch                                                                              latch-                                      (sig- ing     ing     ing   circuit                                                                             ing                                         nal)  circuit circuit circuit                                                                             SWL4  circuit                                                                             remarks                               ______________________________________                                        frame "1"     --      --    OFF   --    "1" data                              1                                       arrived                               frame "1"     "1"     --    OFF   --    three                                 2                                       times.                                frame "1"     "1"     "1"   ON    "1"   "1" data                              3                                       outputted                                                                     at three                                                                      times                                                                         (actuator                                                                     driven)                               frame "0"     "1"     "1"   OFF   "1"   "0" data                              4                                       arrived                               frame "0"     "0"     "1"   OFF   "1"   three                                 5                                       times.                                frame "0"     "0"     "0"   ON    "0"   "0" data                              6                                       outputted                                                                     at three                                                                      times                                                                         (actuator                                                                     driven)                               frame " -1"   "0"     "0"   OFF   "0"   incorrect                             7                                       data " -1"                            frame "0"     " -1"   "0"   OFF   "0"   arrived.                              8                                       this                                  frame "0"     "0"     " -1" OFF   "0"   incorrect                             9                                       data " -1"                            frame "0"     "0"     "0"   ON    "0"   not out-                              10                                      putted (not                                                                   latched in                                                                    latched in                                                                    fourth                                                                        latching                                                                      circuit).                             ______________________________________                                    

It should be noted that in the above table a mark "- " represents thatthe node is held at the initial state when an electric power source isturned on and either one of a mark "1" and a mark "0" represents that asafety value is preset for the node. In a case where the shownembodiment of the present invention is applied to the node, the staterepresented by the mark "0" is preset for the node. Alternatively, acircuit condition may be set such that the comparing circuit 318 isactivated only when signals corresponding to three frames are inputtedinto the node at the initial time.

As will be apparent from the above description, according to theembodiment of the present invention, when any error occurs with data tobe transferred from the main controller 2 to the respective nodes 3-1 to3-n and vice versa, each node can detect an occurrence of the error soas to allow incorrect controlling of an actuator due to the dataassociated with the error to be prevented reliably. In addition, thenode can reliably prevent incorrect controlling of the actuator due toerroneous data even in a case where a data error occurs with theerroneous data which can not be detected by usual error checking means.

In the aforementioned embodiment, description has been made as to a casewhere the number of latching circuits of which latching operation iscompared in the comparing circuit in respect of its content is set to 3as represented by the first to third latching circuits 312 to 314.However, the number of latching circuits may be determined arbitrarily.When the node is put in practical use, an adequate numeral isselectively determined within the range wherein requirements forreliability on a controlling operation and a speed of the controllingoperation (response speed) are fully satisfied.

In addition, in the aforementioned embodiment, in a case where contentsof latching operations performed in the respective latching circuits areidentical to each other, data latched in the latching circuit at thefinal stage (third latching circuit 314) are extracted from the node aseffective control data for the corresponding actuator. However, data tobe extracted may basically be extracted from any latching circuit,provided that the data to be extracted are data which are latched in alatching circuit of which latching operation is compared in respect ofits content.

Additionally, in the aforementioned embodiment (particularly, asillustrated in Table 2), it is supposed that data constituting the datarow DATA representative of a signal (frame signal) to be transferredbetween the respective nodes for controlling each actuator comprise onebit. However, such data structure as mentioned above may be determinedarbitrarily. The embodiment of the present invention may equally beapplied to control data comprising plural bits.

Further, in the aforementioned embodiment, as shown in FIG. 1, it isassumed that the serial control apparatus is constructed such that themain controller and the respective nodes are serially connected in aloop-shaped configuration. Alternatively, the embodiment of the presentinvention may equally be applied to the serial control apparatus whereinthe respective nodes are serially connected to the main controller in arow-shaped configuration (daisy chain-shaped configuration).

A frame pattern representative of signals as shown in FIG. 4, FIG. 5 andFIG. 2 and a protocol for receiving and transmitting signals should notbe limited to those shown in these drawings. Any other pattern of framestructure and protocol may be employed, provided that it is proven thatextraction of control data is accomplished reliably. After all,according to the present invention, all the nodes serially connected toeach other via the main controller in a loop-shaped configuration orserially connected to the main controller in a row-shaped configuration(daisy chain-shaped configuration) include at least means for properlyextracting control data in response to a signal, a plurality of latchingmeans for latching the control data extracted each time the signalhaving the control data included therein is inputted into the relevantnode, while successively shifting the latched control data, comparingmeans for simultaneously comparing contents of the control data latchedby the latching means with each other to output a predeterminedcoincidence signal when it is found that all the compared contents areidentical to each other, and means for separately extracting contents ofthe data latched by the latching means as effective control data foractuating a plurality of corresponding actuators when the coincidencesignal is outputted from the comparing means, respectively. In a casewhere error latching means is added to each node, selection of thelatching means may be made arbitrarily.

It should be noted that, with the serial control apparatus wherein adanger of causing data abnormality as mentioned above in the foregoingparagraphs (a) and (b) need not be taken into account, it suffices thattwo latching means, i.e, first and second latching means (referring toFIG. 3, a data latch 311 is considered as first latching means and afirst latch 312 is considered as second latching means so that an outputfrom the first latch 312 is directly added to the driver 316) areincluded in a signal passage by way of which data extracted at each nodeare fed to each driver for a plurality corresponding terminal units(actuators) and, in a case where an error or an error history isdetected when the extracted data are to be transferred further, a datalatching operation to be performed by the latching means disposed on thedriver side (first latch 312) is inhibited so as not to allow erroneousdata or uncertain data to be fed to the driver.

FIG. 6 to FIG. 8 illustrate a data extracting circuit in accordance withother embodiment of the present invention. In this embodiment, a countercircuit is substituted for an array of latching circuits as mentionedabove. In a case where the serial control apparatus to which thisembodiment is applied is constructed as illustrated in FIG. 1, thecounter circuit is arranged in the same manner as in the embodimentshown in FIG. 3 to FIG. 5.

FIG. 6 is a circuit diagram which illustrates an input section intowhich data frame signals are inputted at the nodes (3-1 to 3-n) eachincluding actuators of which number is represented by k. Also in thissection, a plurality of data frame signals each having a same datacontent are repeatedly received by N times.

Referring to FIG. 6, serial data frame signals sent from the maincontroller 2 or the node at the preceding stage (see FIG. 2) are addedto a synchronization detecting circuit 321, a clock separating circuit322, an error detecting circuit 323, an error history extracting circuit324 and a plurality of switch circuits 325-1 to 325-k corresponding toeach of the k actuators, respectively.

The synchronization detecting circuit 321 serves to detect a time slotassociated with data bit signals dl to dk distributed to the k actuatorscorresponding to the present node from the data row DATA included in theframe signal (which is considered to be, e.g., a CMI coded framesignal). A signal representative of the time slot associated with thedetected data bit signals is added to a shift logic circuit 326.

The clock separating circuit 322 serves to reproduce a clock signal fromthe foregoing frame signal, and the reproduced clock signal is added tothe shift logic circuit 326.

The error checking circuit 323 is adapted to perform, e.g., a CRCchecking operation based on the error check code ERC included in theframe signal. When it detects a data error, it raises a detection outputCR up to a logical high level.

The error history extracting circuit 324 serves to read a history of theerror detected in the node at the preceding stage based on the errorcode R included in the frame signal. When it is found that an error ispresent, the error history extracting circuit 324 raises a detectionoutput ER up to a logical high level.

The detection output CR derived from the error detecting circuit 323 andthe detection output ER derived from the error history extractingcircuit 324 are added as error signals to each of k collating blocks328-1 to 328-k via an OR circuit OR.

When a signal representative of a time slot associated with therespective data bit signals d1 to dk detected in the synchronizationdetecting circuit 321 as well as a clock signal separated in a clockseparating circuit 322 are inputted into the shift logic circuit 326,clock bit signals b1 to bk are successively delivered to the respectiveswitch circuits 325-1 to 325-k and the respective collating blocks 328-1to 328-k in synchronization with the clock signal per each time slotassociated with the respective data bit signal d1 to dk.

When a data bit signal d1 in the form of a frame signal is inputted intothe switch circuit 325-1, a clock bit signal b1 is inputted into theswitch circuit 325-1 which in turn is closed in response to the clockbit signal b1, whereby the data bit signal d1 is delivered to thecollating block 328-1. Subsequently, when data bit signals d2 to dk eachin the form of a frame signal are inputted into other switch circuits325-2 to 325-k in the same manner as mentioned above, clock bit signalsb2 to bk are inputted into the switch circuits 325-2 to 325-k which inturn are closed in response to the clock bit signals b2 to bk, wherebythe respective data bit signals d2 to dk are delivered to othercollating blocks j28-2 to 328-k.

Therefore, the respective data bit signals d1 to dk and the respectiveclock bit signals b1 to bk are distributed and added to the respectivecollating blocks 328-1 to 328-k. Delivery of signals to the collatingblocks 328-1 to 328-k is carried out at every time when a data framesignal is transmitted to the data extracting circuit.

Thus, when a data frame signal having a same data content is repeatedlytransmitted to the data extracting circuit by N times, same N data bitsignals d1 to DN as shown in FIG. 8 are successively added to, e.g., thecollating block 328-1 and thereby N clock bit signals b1 are likewiseadded to the collating block 328-1. When an error or an error history isdetected from the relevant frame signal, an error signal having alogical high level is added to the collating block 328-1.

The collating blocks 328-1 to 328-k are constructed as illustrated inFIG. 7, respectively. Here, description will be typically made on anoperation to be performed by the collating block 328-1.

The respective data bit signals d1-1 to d1 - dN shown in FIG. 8 aresuccessively added to a first latching circuit 81 at every time when adata frame signal is transmitted to the data extracting circuit. Thiscauses the clock bit signal b1 to be successively added to the firstlatching circuit 81 and a determination logic circuit 82. The errorsignal is raised up to a logical high level when an error or an errorhistory is detected, as mentioned above. Then, the error signal is addedto the determination logic circuit 82.

The determination logic circuit 82 serves to deliver an enabling signalto a second latching circuit 83 and an output latching circuit 84. Inaddition, the determination logic circuit 82 serves to deliver a counterclock signal, a count-up signal, a count-load signal and a count-clearsignal to a counter 85 in synchronization with the clock bit signal b1.

Now, it is assumed that the count clear signal is added to the counter85 from the determination logic circuit 82, e.g., at a time point Tshown in FIG. 8. This causes the count value derived from the counter 85to be cleared (initialized), resulting in the count value being reducedto a level of zero.

Thereafter, the first clock bit signal b1 is inputted into the firstlatching circuit 81 in the form of an enabling signal so that the firstdata bit signal d1 - 1 is latched in synchronization with the firstclock bit signal b1. At this time, if an error or an error history isnot detected with respect to the frame signal including the first bitsignal d1 - 1, the error signal is held at a logical low level.

After the count-clear signal is delivered to the counter 85 from thedetermination logic circuit 85 in the above-described manner, the firstclock bit signal b1 is inputted into the determination logic circuit 82.If it is found immediately after inputting of the first clock bit signalb1 in that way that the error signal is held at a logic low level, thecount-load signal is added to the counter 85.

When the count-load signal is inputted into the counter 85, a "1"generating circuit 89 is loaded with a value "1" as a count value whichindicates a count vale "1".

Next, the determination logic circuit 82 adds an enable signal to thesecond latching circuit 83.

When the enabling signal is inputted into the second latching circuit83, the first data bit signal d1 - 1 transmitted from the first latchingcircuit 81 is latched in the second latching circuit 83. Thus, at thistime, the first data bit signal has been latched in the both first andsecond latching circuits 81 and 83.

Next, the second data bit signal d1 - 2 is latched in the first latchingcircuit 81. At this time, the determination logic circuit 82 stops todeliver an enabling signal to the second latching circuit 83, wherebythe first data bit signal d1 - 1 is kept latched in the second latchingcircuit 83.

A data comparing circuit 86 compares the first data bit signal d1 - 1 inthe second latching circuit 83 with the second data bit signal d1 - 2 inthe second data bit signal d1 - 2. If it is found that the both data bitsignals coincide with each other, a signal representative of anoccurrence of the coincidence is added to the determination logiccircuit 82.

When the foregoing both data bit signals are inputted into thedetermination logic circuit 82, the determination logic circuit 82 addsa count-up signal to a counter 85. Then, when the count-up signal isinputted into the counter 85, the counter 85 advances the count valuewhich has assumed "1" up to this time by a value of "1" to reach a countvalue of "2".

Similarly, the preceding data bit signal in the first latching circuit81 and the preceding data bit signal in the second latching circuit 83are compared with each other at every time when third and subsequentdata bit signals, i.e., data bit signals d1-3 to d1-N are latched in thefirst latching circuit 81. When it is found that the foregoing data bitsignals coincide with each other, the counter 85 advances the countvalue by a value of "1".

Therefore, in a case where the third and subsequent data bit signals,i.e., the data bit signals d1-2 to d1-N coincide with the preceding databit signal by m times (where m is equal to or smaller than N), thecounter 85 assumes a count value represented by a value m. Here, itshould be added that the count value m is preset in a value settingcircuit 87.

A comparator 88 compares the count value derived from the counter 85with the value m derived from the m value setting circuit 87. When it isfound that the count value coincides with the value m, i.e., the countvalue reaches the value m, the comparator 88 adds a signal indicative ofan occurrence of the coincidence to the determination logic circuit 82.

When the foregoing signal is inputted into the determination logiccircuit 82, the determination logic circuit 82 adds an enabling signalto an output latching circuit 84 and moreover adds a count-clear signalto the counter 85.

When the foregoing enabling signal is inputted into the output latchingcircuit 84, the output latching circuit 84 latches in the secondlatching circuit 83 the data bit signal which has been latched at thattime so that the data bit signal is outputted from the output latchingcircuit 84 as output data. In addition, when the count-clear signal isinputted into the counter 85, the counter 85 clears the count valuewhich in turn is reduced to a level of zero.

Specifically, when it is found that a (m-1) number of data bit signalsamong the second and subsequent data bit signals, i.e, the data bitsignals d1-2 to d1-N coincide with the preceding data bit signal,respectively, it is considered that the data bit signals d1 which havebeen repeatedly transmitted by times are a correct signal, respectively,whereby the data bit signal which has been latched in the secondlatching circuit 83 at that time is outputted therefrom as output datavia the output latching circuit 84. The output data are added to oneactuator A1 in the present node so as to allow the actuator A1 to beactuated.

Next described is a case where either one of an error and an errorhistory is detected by the error detecting circuit 323 and the errorhistory extracting circuit 324 with the error signal during an operationfor receiving the frame signal in the error detecting circuit 323 andthe error history extracting circuit 324 shown in FIG. 6. In this case,it is assumed that the error signal is raised up to a logic high level.

In this case, the data bit signal d1-(i-1) included in the precedingframe signal is latched in the second latching circuit 83, while thedata bit signal d1-i included in the frame signal is latched in thefirst latching circuit 81 of the collating block 328-1. Then, the databit signals in the first latching circuit 81 and the second latchingcircuit 83 are compared with each other in the data comparing circuit86. Since the error signal is held at the logic high level at this time,the determination logic circuit 82 does not add any count-up signal tothe counter 85 irrespective of results derived from the comparison inthe data comparing circuit 86. For the reason, the counter 85 does notcount up the count value. In this case, the determination logic current82 does not add any enabling signal to the second latching circuit 83.

Specifically, in a case where either one of an error and an errorhistory is not detected with one of the frame signals generated within mtimes while the frame signals each having a same data content arerepeatedly received by N times, the counter 85 does not update the countvalue without any comparative collation with respect to the data bitsignal included in each frame signal. Consequently, even though repeatedreceipt of the data frame signals each having a same data content by mtimes is completed, the count value derived from the counter 85 does notreach a value m. For the reason, a signal indicating that the countvalue reaches the value m is not outputted to the determination logiccircuit 82. Therefore, any enabling signal is not outputted from thedetermination logic circuit 82 to the output latching circuit 84, andthe data bit signal latched in the second latching circuit 84 is notoutputted as output data via the output latching circuit 84. Thus, ifeither one of an error and an error history is detected with the framesignal, the data bit signal included in the frame signal is consideredas an erroneous signal without any processing to be performed for thedata bit signal.

In a case where the data bit signal d1-i is considered as an erroneoussignal, an error code ER indicative of an error is generated in therelevant node so that a frame signal inclusive of the error code ER isdelivered to the node at the subsequent stage or the main controller 2.

Next, description will be made below as to a case where while the countvalue derived from the counter 85 does not reach the value m, the databit signal latched in the first latching circuit 81 is different, fromthe data bit signal latched in the second latching circuit 83 andmoreover an error or an error history is not detected from the framesignal including a data bit signal latched in the first latching circuit81.

In this case, a signal indicating that the data bit signal latched inthe first latching circuit 81 is different from the data bit signallatched in the second latching circuit 83 is inputted into thedetermination logic circuit 82 and moreover a signal indicating that theerror signal held at the logical low level (indicating that no erroroccurs) is inputted into the determination logic circuit 82. In responseto these signals, the determination logic circuit 82 delivers anenabling signal to the second latching circuit 83 and forcibly deliversa count load signal to the counter 85 so as to allow the count value toassume a value of "1".

When the enabling signal is inputted into the second latching circuit83, the second latching circuit 83 latches the data bit signal d1-ilatched in the first latching circuit 81. When the count-load signal isinputted into the counter 85, the counter 85 is loaded with a value "1"derived from the "1" value generating circuit 89 and indicates thisvalue "1" as a count value.

Thereafter, a subsequent data bit signal is latched in the firstlatching circuit 81 every time the data bit signal is transmitted fromthe first latching circuit 81, and when the data bit signal latched inthe first latching circuit 81 is coincident to the data bit signallatched in the second latching circuit 83, the counter 85 counts up thecount value by a value of "1". When the count value derived from thecounter 85 reaches the value m, the data bit signal latched in thesecond latching circuit 83 is outputted as output data via the outputlatching circuit 84.

Specifically, in a case where the count value derived from the counter85 does not reach the value m, the data bit signal latched in the firstlatching circuit 81 is different from the data bit signal latched in thesecond latching circuit 83 and moreover an error or an error history isnot detected with the frame signal including the data bit signal latchedin the first latching circuit 81, this represents that communicationwith the frame signal having the same data content as that of thoseavailable up to this time is shifted to communication with the framesignal having other data content rather than the foregoing one. To thisend, the data bit signal latched in the first latching circuit 81 isthen latched in the second latching circuit 83 and the counter 85 setsthe count value to a value "1", whereby the counter 85 is ready toreceive a signal subsequent to the frame signal having the other datacontent which has been shifted in that way.

While the collating block 328 - 1 has been typically described above,other collating blocks 328 - 2 to 328 - k of course operate in the samemanner as the collating block 328 - 1. In detail, the other collatingblocks 328 - 2 to 328 - k operate such that the data bit signals d2 todk and the clock bit signals b2 to bk are repeatedly inputted thereintoto carry out collation with the data bit signals, respectively. When thecount value reaches the value m, the data bit signals d2 to dk areoutputted to a corresponding actuator as output data, respectively.

In this manner, according to this embodiment of the present invention,the data bit signals which have been successively inputted in the dataextracting circuit can comparatively be collated merely by arranging thefirst latching circuit and the second latching circuit. Therefore, evenin a case where the number of data bit signals to be compared with eachother (times of comparing operations) need to be increased, a scale ofcircuit arrangement may be reduced. In addition, it is possible toeasily vary many items, such as times of comparing operations, i.e.,reliability on controlling operations, response speed to controllingoperation or the like item merely by properly varying the value m whichhas been set in the m value setting circuit. The more the number ofcomparing operations increases, the more the reliability on controllingoperations increases. . Further, the smaller the number of comparingoperations becomes, the more the responsiveness to controlling operationis increased. In practical use, times of comparing operations, i.e., thevalue m is adequately set within the range that the foregoing items arefully satisfied.

It should be noted that illustration of the start code detectingcircuit, the stop code detecting circuit and others are eliminated fromthe drawing of FIG. 6 for the purpose of simplification.

Not only in the first embodiment bust also in the second embodiment asmentioned above, the present invention is equally applicable to controldata included in frame signals for actuators as well as input datatransferred from sensors, i.e., input data transferred from each nodeassociated with the main controller 2. In this case, while data bitsignals indicative of input data are repeatedly inputted from sensors(at each node) into the main controller 2, the first data bit signal islatched in the first latching circuit and subsequent data bit signalsare latched in the second latching circuit. When the data bit signallatched in the first latch circuit coincides with the data bit signallatched in the second latching circuit signal by a single time or byplural times, these data bit signals are considered as true sensor dataand they are then formally received in the main controller 2.

If a trouble of line disconnection takes place for some reason in aloop-shaped signal transmission line extending between the present nodeand other node in the serial control apparatus as shown in FIG. 1,signals transferred from nodes on the upstream side can not be receivedby the serial control apparatus for a period of time longer than apredetermined one, whereby actuators corresponding to the present nodeare brought in the operative state before the trouble of linedisconnection takes place in that way. Since a signal transmission lineextending to the main controller from nodes on the upstream side wherethe trouble of line disconnection takes place is held in a normal state,actuators corresponding to the nodes on the upstream side arecontinuously actuated in response to signals from the main controller.This means that the whole system holds in a mixed state the nodes whichnormally operate in response to signals from the main controller and thenodes of which operation is stopped in the operative state before thetrouble of line disconnection takes place. Consequently, an operation tobe realized in combination with operations to be performed in all thenodes undesirably becomes an erroneous operation. This leads to apossibility that a trouble in the form of damage or breakage takes placewith the serial control apparatus itself or objects to be controlled.

Next, FIG. 9 to 17 illustrate a data extracting circuit in accordancewith another embodiment of the present invention, wherein damage orbreakage of the serial control apparatus or objects to be controlled caneffectively be prevented even when a troublesome line disconnectiontakes place.

First, an outline of this embodiment will be described with reference toFIG. 9.

The main controller 2 shown in FIG. 1 delivers a frame signal to thesignal transmission line 1 in the above-described manner, wherein theframe signal includes a start code ST at the head end, a control datarow DATA for each node at the subsequent location, a stop code SPindicative of the end of the control data row at the subsequent locationand an error check code ERC such as a parity check code, a CRC code orthe like at the tail end, as shown in FIG. 9(a).

When troublesome line disconnection takes place for some reason betweenthe present node and the signal transmission line 1, the respectivenodes 3 - 1 to 3 - n inform the main controller 2 via nodes on thedownstream side that the troublesome line disconnection has taken place.

For example, in a case where a troublesome line disconnection takesplace at a position on the signal transmission line 1 between the node3 - 2 and the node 3 - 1 shown in FIG. 1, the node 3 - 2 delivers aninformation on the line disconnection in the form of a frame signalcomprising a line disconnection code BEK and a line disconnectionposition code NO. (0) to the main controller 2 via the nodes 3 - 3 to3 - n on the downstream side, as shown in FIG. 9(b).

The information on the line disconnection is received by the nodes 3 - 3to 3 - n on the downstream side. When the nodes 3 - 3 to 3 - n receivethe information on the line disconnection, respectively, a plurality ofactuators A1 to Ak associated with the present node are forciblyactuated toward the safe side and then the present node updates the linedisconnection position code NO. (0) by a value of "1" so that theupdated code is transmitted further to the nodes on the downstream side.Consequently, an information on the line disconnection with the linedisconnection position code shifted to "NO. (n-2)" as shown in FIG. 9(c)is transmitted from the node 3 - n on the ultimate downstream side andthen inputted in the main controller 2.

In view of the fact that the line disconnection code has been shifted to"NO. (n-2)", the main controller 2 recognizes that the linedisconnection takes place at a position just before the node 3 - 2 atthe second stage as viewed from the upstream side and then sends to thenode 3 - 1 on the upstream side an information for actuating theactuators A1 to Ak toward the safe side, i.e., an information of DATA=0,as shown in FIG. 9(d). This causes a plurality of actuators A1 to Akassociated with the node 3 - 1 to be actuated toward the safe side inthe same manner as in the nodes 3 - 3 to 3 - n. In addition, the node3 - 2 that is a signal supply source for sending an information on theline disconnection operates such that a plurality of actuators A1 to Akassociated with the node 3 - 2 are actuated toward the safe side.

As a result, an operation of the system is interrupted while the systemis held in the operative state wherein a number of actuators A1 to Akassociated with all the nodes are actuated toward the safe side.

Here, it should be noted that an occurrence of the line disconnectioncan easily be detected by the fact that no communication information issent from nodes on the upstream side (main controller in a case of thenode on the ultimate upstream side) for a period of time longer than apredetermined one. In a case where the trouble of line disconnectiontakes place at a position just before the node 3 - 2 as shown in FIG. 1,the main controller transitionally carries out detection on theassumption that a line disconnection takes place in the nodes 3 - 3 to3 - n. However, finally, the main controller determines the node 3 - 2as an information supply source for sending an information on the linedisconnection. Therefore, other nodes 3 - 3 to 3 - n are released fromthe operative state wherein the line disconnection is reliably detected.

FIG. 10 is a block diagram which illustrates by way of example the innerstructure of each of the nodes 3 - 1 to 3 - n in an undesirable statewherein a line disconnection takes place. With the node structure asshown in the drawing, a frame signal sent from a certain node on theupstream side is received by an input circuit 330. In a case where theframe signal is modulated in the form of, e.g., a CMI code or the likecode and then transmitted further, the input circuit 330 is constructedin a circuit structure such that the frame signal is demodulated in theform of a NRZ code. The demodulated signal is outputted to a dataprocessing circuit 331 (inclusive of a data extracting circuit andothers as shown in the aforementioned embodiment), a line disconnectiondetecting circuit 332, a line disconnection code detecting circuit 333and an error determining circuit 334.

Basically, the data processing circuit 331 operates such that only dataor a data row DATA for the present node are extracted from the data rowDATA for all the node included in the demodulated frame signal, they areheld in a latching circuit 335, thereafter, output signals from sensorsS1 to Sn are inserted in a time slot associated with the present nodeand they are modulated in an output circuit 336 again so as to allow thedemodulated output signals to be sent to nodes on the downstream side.The latching circuit 335 serves to deliver the thus held data or datarow to an actuator driving signal generating circuit (driver) 339 viagates 337 and 338 so as to drive a plurality of actuators A1 to Ak.

On the other hand, the error determining circuit 334 serve to determinepresence or absence of an error with the received data row DATA by usingthe error check code ERC. When the error determining circuit 334 findspresence of an error, it opens the gate 337 to inhibit data or a datarow from being inputted into the actuator driving signal generatingcircuit 339 from the latching circuit 335.

In a case where the line disconnection detecting circuit 332 does notreceive a frame signal from nodes on the upstream side for a period oftime longer than a predetermined one which is set by a timer (notshown), the line disconnection detecting circuit 332 determines that theline disconnection takes place at a position upstream of the presentnode. Then, the data processing circuit 331 generates an information onthe line disconnection in a frame structure as shown in FIG. 9(b) sothat the information is sent to nodes on the downstream side via theoutput circuit 336. In addition, a signal indicative of detection ofline disconnection is inputted into the line disconnection detectingcircuit 332 as an inhibition input via an OR gate OR3. At this time,when it is found that a gate (AND gate) 338 is kept opened, the linedisconnection detecting circuit 332 operates to close the AND gate 338,as is apparent from time charts shown in FIG. 11, whereby driving of theactuators A1 to Ak is interrupted. In other words, when the drivingsignal disappears, the actuators A1 to Ak are actuated toward the safeside until their actuation stops.

On the other hand, in a case where the line disconnection detectingcircuit 332 receives an information on the trouble of line disconnectionin a frame structure as shown in FIG. 9(b), the line disconnectiondetecting circuit 332 detects a line disconnection code BRK in theinformation on the trouble of line disconnection and recognizes that thetrouble of line disconnection takes place at a position upstream of thepresent node so that a signal equivalent to the line disconnectiondetecting signal derived from the line disconnection detecting circuit332 is inputted into the OR gate OR3 to stop driving of the actuators A1to Ak.

FIG. 12 is a block diagram which illustrates by way of example the innerstructure of the main controller 2 in accordance with this embodiment ofthe present invention. With this structure of the main controller 2, aframe signal from the node 3 - n on the ultimate downstream side isreceived in an input circuit 201. In a case where the frame signal ismodulated in the form of a CMI code or the like code and transmittedfurther, the input circuit 201 is constructed in a circuit structuresuch that the modulated frame signal is demodulated in the form of a NZRcode. The demodulated frame signal is inputted into a frame processingcircuit 202, a line disconnection detecting circuit 203 and a linedisconnection code detecting circuit 204.

The frame processing circuit 202 operates in such a manner as to monitorthe present state of all the nodes with reference to sensor outputsignals from all the nodes included in the demodulated frame signal,determine a control data row DATA for all the nodes to advance theprocess to a next step, generate a frame signal having a frame structureas shown in FIG. 9(a) in a normal frame generating circuit 205 and theninput the frame signal into an output circuit 207 via a switch 206. Theinputted frame signal is converted into a CMI code or the like code inthe output circuit 207 and the converted frame signal is transmitted tothe node 3 - 1 on the ultimate upstream side.

In a case where no frame signal is inputted into the line disconnectiondetecting circuit 203 from the node 3 - n on the ultimate downstreamside for a period of time longer than a predetermined one, as is oftenthe case where the line disconnection detecting circuit 332 operates forthe nodes 3 - 1 to 3 - n in that way, the wire disconnection circuit 203determines that the trouble of line disconnection takes place at aposition between the node 3 - n and the main controller 2. Then, theline disconnection detecting circuit 203 generates a frame signal havinga frame structure as shown in FIG. 9(d) in a stop frame generatingcircuit 208 so that the line disconnection detection signal is inputtedinto a switch 206 via an OR gate OR4 to shift the switch 206 to aposition "2" where the frame signal is transferred further via theoutput circuit 207. The foregoing is equally applicable to a case wherethe line disconnection code detecting circuit 204 detects a frame signalincluding a line disconnection code BRK from the node 3 - n.

FIG. 13 illustrates a plurality of time charts which representoperations of each section at the time when a trouble of linedisconnection takes place for some reason.

It should be noted that in place of a case where the control data rowDATA for all the nodes is set to "0" to send a frame signal as shown inFIG. 9(d), an information having the same frame structure as that shownin FIG. 9(d) on a trouble of line disconnection may be generated andthen delivered so as to allow a plurality of corresponding actuatorsupstream of a location where the line disconnection takes place to beactuated toward the safe side.

FIG. 14 is a block diagram which illustrates by way of example anotherstructure of the main controller 2 which is constructed such that theinformation on line disconnection, as shown in FIG. 9(b), is generatedand delivered. In this case, the main controller 2 is provided with aline disconnection frame generating circuit 209 which is substituted forthe stop frame generating circuit 208 shown in FIG. 12. In addition, themain controller 2 is provided with a line disconnection code numberdetermining circuit 210 which determines that a line disconnectionposition code is set lower than "n-1".

When it is assumed that the line disconnection takes place at a positionbetween the node 3 - 1 and the node 3 - 2, a communication informationrepresentative of a line disconnection code n - 2 is inputted into themain controller 2 from the node 3 - n on the ultimate downstream side,as shown in FIG. 15. Then, the main controller 2 operates such that aninformation on the line disconnection represented by a linedisconnection position code=0 is generated in the line disconnectionframe generating circuit 209 and then delivered to the main controller 2so as to allow a plurality of actuators A1 to Ak associated with thenode 3 - 1 to be actuated toward the safe side, as shown in FIG. 15.

Thus, the actuators A1 to Ak associated with the node 3 - 1 are actuatedtoward the safe side until their actuation is stopped.

When the line disconnection which has taken place between the node 3 - 1and the node 3 - 2 is repaired while the foregoing state is maintainedso that a normal condition of the system is resumed, the information onthe line disconnection transmitted from the main controller 2 returns tothe main controller 2 via the nodes 3 - 1 to 3 - n. At this time, themain controller 2 updates the present line disconnection code to "n". Aslong as the line disconnected state is continuously maintained, the linedisconnection position code representative of the trouble of linedisconnection to be inputted into the main controller 2 is set lowerthan n-1 without fail. Then, the line disconnection code numberdetermining circuit 210 determines that the present line disconnectionposition code is held lower than "n-1". Once the line disconnection codenumber determining circuit 210 has determined that the linedisconnection code is held lower than "n-1", the main controller 2recognizes that the trouble of line disconnection still remains at acertain position along the signal transmission line 1. Then, the maincontroller 2 opens an AND gate 211 disposed between a line disconnectioncode detecting circuit 204 and an OR gate OR4 shifts a switch 206 to aposition "2" and sends from an output circuit 207 the information on theline disconnection which has been generated in the line disconnectionframe generating circuit 209.

In a case where the line disconnection position code is identified by"n", an information on the line disconnection which has been sent fromthe present node is unavoidably brought back to the present node. Inthis case, the main controller 2 recognizes that the line disconnectionis properly repaired to assume a correct condition and then closes theAND gate 211 so that delivery of the information on the now repairedline is stopped.

FIG. 17 shows a plurality of time charts which illustrate operations tobe performed by the respective circuits associated with the maincontroller shown in FIG. 14, respectively.

Each of the aforementioned embodiments has been described as to a casewhere delivery of a driving signal to a plurality of actuators Al to Akis interrupted in the event of line disconnection. However, with respectto actuators of which safety side is held in a driving state, it shouldof course be understood that they may be constructed such that they arebrought in a continuous driving state in the event of linedisconnection. To this end, an OR gate needs to be substituted for thegate 338 (see FIG. 10).

In addition, the embodiment shown in FIG. 9 to FIG. 17 of course mayarbitrarily be combined with the embodiment shown in FIG. 3 to FIG. 5 orthe embodiment shown in FIG. 6 to FIG. 8. Such combination as mentionedabove assures that a safe operation of the serial control apparatus isreliably maintained no matter what operative state is assumed by theserial control apparatus.

INDUSTRIAL APPLICABILITY

As will be apparent from the above description, according to the presentinvention, the data extracting circuit can reliably prevent erroneousdata of which occurrence is anticipated with the serial controlapparatus from being received in the serial control apparatus. Inaddition, the data extracting circuit can reliably prevent the serialcontrol apparatus itself and objects to be controlled from beingundesirably damaged or injured due to an incorrect operation of thewhole system. Thus, employment of the data extracting circuit of thepresent invention assures that a serial control apparatus having a highreliability can be realized.

We claim:
 1. A data extracting circuit employable for a serial controlapparatus including a main controller and a plurality of nodes eachserving as an auxiliary controller, said main controller and said nodesbeing serially connected in a loop-shaped configuration or in a daisychain-shaped configuration by a signal transmission line, said serialcontrol apparatus being provided with at least one of time serial dataincluding control data repeatedly periodically transmitted from saidmain controller to all nodes serially connected to said main controllervia said signal transmission line and time serial data including sensingdata repeatedly periodically transmitted from a specific one of saidplurality of nodes to said main controller and all nodes seriallyconnected to said specific node via said signal transmission line, saiddata extracting circuit being disposed in said main controller and ineach of said plurality of nodes and serving to extract a data historywith respect to said time serial data being repeatedly periodicallytransmitted, said data extracting circuit comprising:extracting meansfor extracting data in a specific time slot of said time series data,first latching means for latching said extracted data as new data eachtime said extracting means extracts data, second latching means forlatching as old data the data latched by said first latching means inresponse to subsequent transmissions of said time series data,controlling means for controlling a terminal unit in response to thedata latched by said second latching means, detecting means fordetecting from said time series data presence or absence of an error andpresence or absence of an error history representing that an error ispresent in said time series data, and inhibiting means for inhibitingdata from being latched by said second latching means when at least oneof the error and the error history is detected by said detecting means.2. A data extracting circuit employable for a serial control apparatusas claimed in claim 1, whereinsaid second latching means comprises ashift register having a plurality of stages constituting a plurality ofserially connected latching means for shifting said old data from saidfirst latching means sequentially from one stage to a next stage of saidplurality of stages each time said time series data are transmitted andfor respectively latching the data being shifted, and wherein said dataextracting circuit further includes; comparing means for simultaneouslycomparing contents of the respective stages of said shift registerconstituting said second latching means with each other and outputting acoincidence signal when all the contents coincide with each other, andmaintaining means for maintaining contents of the data inputted fromsaid second latching means to said controlling means until saidcoincidence signal is outputted from the comparing means.
 3. A dataextracting circuit employable for a serial control apparatus as claimedin claim 1, further including;comparing means for comparing contents ofdata latched by said first and second latching means with each other andoutputting a coincidence signal when said contents of the latched datacoincide with each other, counting means for counting the number ofcoincidence signals each time said coincidence signal is outputted fromsaid comparing means, and determination controlling means for allowingthe data being latched in said second latching means to be inputted intosaid controlling means when the count value counted in said countingmeans reaches a predetermined value and initializing the count valuecounted in said counting means.
 4. A data extracting circuit employablefor a serial control apparatus as claimed in claim 3, wherein saiddetermination controlling means further includes;first count controllingmeans for controlling to reset said count value counted in said countingmeans so as to forcibly set a first count value when the contents ofdata latched in said first latching means are different from thecontents of data latched in said second latching means.
 5. A dataextracting circuit employable for a serial control apparatus as claimedin claim 4, wherein said determination controlling means furtherincludes;second count controlling means for controlling to reserve saidcount value counted in said counting means when at least one of theerror and the error history is detected by said detecting means.
 6. Adata extracting circuit employable for a serial control apparatus asclaimed in claim 1, wherein said main controller and said plurality ofnodes are serially connected in the loop-shaped configuration,whereineach of said nodes includes; means for extracting data relativeto one node among from the time serial data transmitted from said maincontroller, means for controlling a terminal unit connected to the onenode, and means for sending data outputted from said terminal unit byinserting said output data into a time slot assigned to the one node tosaid main controller via other nodes located on a downstream side withrespect to a data transmission direction, and wherein each of said dataextracting means in said main controller and each node includes; linedisconnection detecting means for detecting that a trouble of linedisconnection takes place on said signal transmission line, informingmeans for generating information on the trouble of line disconnection inresponse to a line disconnection detecting signal from said linedisconnection detecting means to inform that the trouble takes place onsaid signal transmission line, said informing means in each nodeinforming said main controller via nodes located on the downstream sidewith respect to the data transmission direction of the trouble of linedisconnection and said informing means in said main controller informingnodes located on an upstream side with respect to the data transmissiondirection of a location where the trouble of line disconnection hastaken place via a part of the signal transmission line without any linedisconnection caused thereon, and line disconnection controlling meansfor forcibly actuating toward a safe side said terminal unit toward apreviously set fail-safe side on the basis of at least either one ofconditions when said line disconnection detecting signal is outputtedfrom the line disconnection detecting means and when said information onthe trouble of line disconnection delivered from nodes located on theupstream side with respect to the data transmission direction isreceived by said line disconnection controlling means.
 7. A dataextracting circuit employable for a serial control apparatus as claimedin claim 1, wherein said main controller and said plurality of nodes areserially connected in the loop-shaped configuration, whereineach of saidnodes includes; means for extracting data relative to one node amongfrom the time serial data transmitted from said main controller, meansfor controlling a terminal unit connected to the one node, and means forsending data outputted from said terminal unit by inserting said outputdata into a time slot assigned to the one node to transmit said data tosaid signal transmission line and main controller via other nodeslocated on downstream side with respect to a data transmissiondirection, and wherein each of said data extracting means in said maincontroller and each node includes; line disconnection detecting meansfor detecting that a line disconnection has taken place on said signaltransmission line, informing means for generating information on theline disconnection in response to a line disconnection detecting signalfrom said line disconnection detecting means to inform that the linedisconnection has taken place on said signal transmission line, saidinforming means in each node informing said main controller via nodeslocated on the downstream side with respect to the data transmissiondirection of the line disconnection and said informing means in saidmain controller informing nodes located on an upstream side with respectto the data transmission direction of a location where the linedisconnection has taken place via a part of the signal transmission linewithout any line disconnection caused thereon, and line disconnectioncontrolling means for controlling to forcibly drive said inhibitingmeans on the basis of at least either one of conditions when said linedisconnection detecting signal is outputted from the line disconnectiondetecting means and when said information of the line disconnectiondelivered from nodes located on the upstream side with respect to thedata transmission direction is received by said line disconnectioncontrolling means.